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| author | Bastian Koppelmann | 2015-05-07 19:55:37 +0200 |
|---|---|---|
| committer | Bastian Koppelmann | 2015-05-22 17:02:33 +0200 |
| commit | e5c96c82bc529674b61eacd221734abc2674e264 (patch) | |
| tree | 1f868a6fbb25d9bf931752028c2afdac97cb4d8c /target-tricore/translate.c | |
| parent | target-tricore: add SWAPMSK instructions of the v1.6.1 ISA (diff) | |
| download | qemu-e5c96c82bc529674b61eacd221734abc2674e264.tar.gz qemu-e5c96c82bc529674b61eacd221734abc2674e264.tar.xz qemu-e5c96c82bc529674b61eacd221734abc2674e264.zip | |
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
This instruction was introduced by the new Aurix platform.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/translate.c')
| -rw-r--r-- | target-tricore/translate.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index b2e25e7c7f..52f474ba9f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6449,6 +6449,11 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_UNPACK: gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); break; + case OPC2_32_RR_CRC32: + if (tricore_feature(env, TRICORE_FEATURE_161)) { + gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); + } /* TODO: else raise illegal opcode trap */ + break; } } |