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| author | Bastian Koppelmann | 2015-01-19 16:43:07 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2015-01-27 12:48:02 +0100 |
| commit | 0953225588ee30de2e92485331ad1bb3d7c7d089 (patch) | |
| tree | dc174613fe64f12f8c704c4c5de9f1e79f131957 /target-tricore/tricore-opcodes.h | |
| parent | target-tricore: Add instructions of RRPW opcode format (diff) | |
| download | qemu-0953225588ee30de2e92485331ad1bb3d7c7d089.tar.gz qemu-0953225588ee30de2e92485331ad1bb3d7c7d089.tar.xz qemu-0953225588ee30de2e92485331ad1bb3d7c7d089.zip | |
target-tricore: Add instructions of RRR opcode format
Add microcode generator function gen_cond_sub.
Add helper functions:
* ixmax/ixmin: search for the max/min value and its related index in a
vector of 16-bit values.
* pack: dack two data registers into an IEEE-754 single precision floating
point format number.
* dvadj: divide-adjust the result after dvstep instructions.
* dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.
OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 82bd161645..baf537f160 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -516,7 +516,7 @@ enum { OPC1_32_RRPW_DEXTR = 0x77, /* RRR Format */ OPCM_32_RRR_COND_SELECT = 0x2b, - OPCM_32_RRR_FLOAT = 0x6b, + OPCM_32_RRR_DIVIDE = 0x6b, /* RRR1 Format */ OPCM_32_RRR1_MADD = 0x83, OPCM_32_RRR1_MADDQ_H = 0x43, |