diff options
| author | Bastian Koppelmann | 2014-10-30 13:06:53 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2014-12-10 12:13:45 +0100 |
| commit | 2b2f7d97d856a4e7020d881ec1e6e60be64d0ab6 (patch) | |
| tree | f1dc2d8d1a7cdcd92782ff64def4b469b2882137 /target-tricore/tricore-opcodes.h | |
| parent | target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format (diff) | |
| download | qemu-2b2f7d97d856a4e7020d881ec1e6e60be64d0ab6.tar.gz qemu-2b2f7d97d856a4e7020d881ec1e6e60be64d0ab6.tar.xz qemu-2b2f7d97d856a4e7020d881ec1e6e60be64d0ab6.zip | |
target-tricore: Add instructions of RLC opcode format
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 9b042e4b37..bafc8fba46 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -192,6 +192,7 @@ #define MASK_OP_RLC_D(op) MASK_OP_META_D(op) #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27) +#define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27) #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op) /* RR Format */ |