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author | Bastian Koppelmann | 2015-05-07 21:25:42 +0200 |
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committer | Bastian Koppelmann | 2015-05-22 17:02:34 +0200 |
commit | bc3551c43308dd77bc1cc9a4e39962b2afd4dffc (patch) | |
tree | c28068a87ee64f3c82e60b992ccbc54b57e97ecd /target-tricore/tricore-opcodes.h | |
parent | target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA (diff) | |
download | qemu-bc3551c43308dd77bc1cc9a4e39962b2afd4dffc.tar.gz qemu-bc3551c43308dd77bc1cc9a4e39962b2afd4dffc.tar.xz qemu-bc3551c43308dd77bc1cc9a4e39962b2afd4dffc.zip |
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
-rw-r--r-- | target-tricore/tricore-opcodes.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 440c7fefed..d1506a9429 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1434,4 +1434,5 @@ enum { OPC2_32_SYS_SVLCX = 0x08, OPC2_32_SYS_TRAPSV = 0x15, OPC2_32_SYS_TRAPV = 0x14, + OPC2_32_SYS_RESTORE = 0x0e, }; |