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| author | Bastian Koppelmann | 2014-12-02 18:22:27 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2014-12-21 19:35:16 +0100 |
| commit | e2bed107c6d1dbde564029ac2bca450cdb3f596e (patch) | |
| tree | e611f5fa0a3066d177d0878b38f98fe78360ab07 /target-tricore/tricore-opcodes.h | |
| parent | target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi... (diff) | |
| download | qemu-e2bed107c6d1dbde564029ac2bca450cdb3f596e.tar.gz qemu-e2bed107c6d1dbde564029ac2bca450cdb3f596e.tar.xz qemu-e2bed107c6d1dbde564029ac2bca450cdb3f596e.zip | |
target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode
Add instructions of RR opcode format, that have 0x4b as the first opcode.
Add helper functions:
* parity: Calculates the parity bits for every byte of a 32 int.
* bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise.
* unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa.
* dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
where the quotient result is guaranteed to fit into 8 bit.
* dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
where the quotient result is guaranteed to fit into 16 bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 17d9ad950b..d66f879a39 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -496,7 +496,7 @@ enum { OPCM_32_RR_LOGICAL_SHIFT = 0x0f, OPCM_32_RR_ACCUMULATOR = 0x0b, OPCM_32_RR_ADRESS = 0x01, - OPCM_32_RR_FLOAT = 0x4b, + OPCM_32_RR_DIVIDE = 0x4b, OPCM_32_RR_IDIRECT = 0x2d, /* RR1 Format */ OPCM_32_RR1_MUL = 0xb3, |