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| author | Bastian Koppelmann | 2015-05-06 20:22:45 +0200 |
|---|---|---|
| committer | Bastian Koppelmann | 2015-05-22 17:02:33 +0200 |
| commit | fcecf12684e1169653df72ed307ec2a82ca69b18 (patch) | |
| tree | fac34edc9d3ce2f92ed5d91c5ebd01528e6d138f /target-tricore | |
| parent | target-tricore: introduce ISA v1.6.1 feature (diff) | |
| download | qemu-fcecf12684e1169653df72ed307ec2a82ca69b18.tar.gz qemu-fcecf12684e1169653df72ed307ec2a82ca69b18.tar.xz qemu-fcecf12684e1169653df72ed307ec2a82ca69b18.zip | |
target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore')
| -rw-r--r-- | target-tricore/translate.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 663b2a0796..1c37e48133 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3485,7 +3485,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, * Functions for decoding instructions */ -static void decode_src_opc(DisasContext *ctx, int op1) +static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1) { int r1; int32_t const4; @@ -3546,6 +3546,12 @@ static void decode_src_opc(DisasContext *ctx, int op1) const4 = MASK_OP_SRC_CONST4(ctx->opcode); tcg_gen_movi_tl(cpu_gpr_a[r1], const4); break; + case OPC1_16_SRC_MOV_E: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + tcg_gen_movi_tl(cpu_gpr_d[r1], const4); + tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); + } /* TODO: else raise illegal opcode trap */ + break; case OPC1_16_SRC_SH: gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); break; @@ -3883,9 +3889,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_16_SRC_LT: case OPC1_16_SRC_MOV: case OPC1_16_SRC_MOV_A: + case OPC1_16_SRC_MOV_E: case OPC1_16_SRC_SH: case OPC1_16_SRC_SHA: - decode_src_opc(ctx, op1); + decode_src_opc(env, ctx, op1); break; /* SRR-format */ case OPC1_16_SRR_ADD: |