diff options
| author | Richard Henderson | 2022-10-11 05:18:48 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-10-20 12:27:49 +0200 |
| commit | 24d18d5d7e31462b7bd5bb2c6ee19856699e34ed (patch) | |
| tree | fe597097b7c4f3b3c80be8222df043957297c62d /target/arm/cpu-param.h | |
| parent | target/arm: update the cortex-a15 MIDR to latest rev (diff) | |
| download | qemu-24d18d5d7e31462b7bd5bb2c6ee19856699e34ed.tar.gz qemu-24d18d5d7e31462b7bd5bb2c6ee19856699e34ed.tar.xz qemu-24d18d5d7e31462b7bd5bb2c6ee19856699e34ed.zip | |
target/arm: Enable TARGET_PAGE_ENTRY_EXTRA
Copy attrs and shareability, into the TLB. This will eventually
be used by S1_ptw_translate to report stage1 translation failures,
and by do_ats_write to fill in PAR_EL1.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu-param.h')
| -rw-r--r-- | target/arm/cpu-param.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 08681828ac..38347b0d20 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -30,6 +30,18 @@ */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 + +/* + * Cache the attrs and shareability fields from the page table entry. + * + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. + * For shareability, as in the SH field of the VMSAv8-64 PTEs. + */ +# define TARGET_PAGE_ENTRY_EXTRA \ + uint8_t pte_attrs; \ + uint8_t shareability; + #endif #define NB_MMU_MODES 8 |