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| author | Richard Henderson | 2022-10-11 05:18:50 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-10-20 12:27:49 +0200 |
| commit | 937f2245596de9026ca8ae017ef47889523c4326 (patch) | |
| tree | ce28803c3bcb9c174a0d3b2a849c5a4a0e44b197 /target/arm/cpu-param.h | |
| parent | target/arm: Use probe_access_full for MTE (diff) | |
| download | qemu-937f2245596de9026ca8ae017ef47889523c4326.tar.gz qemu-937f2245596de9026ca8ae017ef47889523c4326.tar.xz qemu-937f2245596de9026ca8ae017ef47889523c4326.zip | |
target/arm: Use probe_access_full for BTI
Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit.
In is_guarded_page, use probe_access_full instead of just guessing
that the tlb entry is still present. Also handles the FIXME about
executing from device memory.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu-param.h')
| -rw-r--r-- | target/arm/cpu-param.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 38347b0d20..f4338fd10e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -36,12 +36,13 @@ * * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability, as in the SH field of the VMSAv8-64 PTEs. + * For shareability and guarded, as in the SH and GP fields respectively + * of the VMSAv8-64 PTEs. */ # define TARGET_PAGE_ENTRY_EXTRA \ - uint8_t pte_attrs; \ - uint8_t shareability; - + uint8_t pte_attrs; \ + uint8_t shareability; \ + bool guarded; #endif #define NB_MMU_MODES 8 |