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| author | Richard Henderson | 2018-10-24 08:50:16 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-24 08:50:16 +0200 |
| commit | 7e0cf8b47f0e67cebbc3dfa73f304e56ad1a090f (patch) | |
| tree | cbb0ab5deb149ddd90bd356ea39ed0521dca8371 /target/arm/cpu.c | |
| parent | target/arm: Convert v8 extensions from feature bits to isar tests (diff) | |
| download | qemu-7e0cf8b47f0e67cebbc3dfa73f304e56ad1a090f.tar.gz qemu-7e0cf8b47f0e67cebbc3dfa73f304e56ad1a090f.tar.xz qemu-7e0cf8b47f0e67cebbc3dfa73f304e56ad1a090f.zip | |
target/arm: Convert division from feature bits to isar0 tests
Both arm and thumb2 division are controlled by the same ISAR field,
which takes care of the arm implies thumb case. Having M imply
thumb2 division was wrong for cortex-m0, which is v6m and does not
have thumb2 at all, much less thumb2 division.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181016223115.24100-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6f27c33b55..9319f92f1f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -829,7 +829,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - set_feature(env, ARM_FEATURE_ARM_DIV); + assert(cpu_isar_feature(arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -862,12 +862,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } - if (arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } - if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } if (arm_feature(env, ARM_FEATURE_VFP4)) { set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP_FP16); @@ -1388,8 +1382,6 @@ static void cortex_r5_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); - set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_PMSA); cpu->midr = 0x411fc153; /* r1p3 */ |