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| author | Peter Maydell | 2020-03-30 23:04:00 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-05-04 11:32:46 +0200 |
| commit | ce3125bed935a12e619a8253c19340ecaa899347 (patch) | |
| tree | cb34167cf7fc1b8a20a26d6a4740c4fc32368312 /target/arm/cpu.c | |
| parent | target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae() (diff) | |
| download | qemu-ce3125bed935a12e619a8253c19340ecaa899347.tar.gz qemu-ce3125bed935a12e619a8253c19340ecaa899347.tar.xz qemu-ce3125bed935a12e619a8253c19340ecaa899347.zip | |
target/arm: Implement ARMv8.2-TTS2UXN
The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
translation table descriptors from just bit [54] to bits [54:53],
allowing stage 2 to control execution permissions separately for EL0
and EL1. Implement the new semantics of the XN field and enable
the feature for our 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-5-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 141d947775..f588344df8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2686,6 +2686,7 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ cpu->isar.id_mmfr4 = t; } #endif |