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| author | Richard Henderson | 2020-02-07 15:04:21 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-07 15:04:21 +0100 |
| commit | 03c76131bc494366a4357a1d265c5eb5cc820754 (patch) | |
| tree | 96953da4a6a741c7fa815503a30e221583a1da66 /target/arm/cpu.h | |
| parent | target/arm: Define isar_feature_aa64_vh (diff) | |
| download | qemu-03c76131bc494366a4357a1d265c5eb5cc820754.tar.gz qemu-03c76131bc494366a4357a1d265c5eb5cc820754.tar.xz qemu-03c76131bc494366a4357a1d265c5eb5cc820754.zip | |
target/arm: Enable HCR_E2H for VHE
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a53f5d09b..0e68704a90 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1424,13 +1424,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) |