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author | Richard Henderson | 2018-10-24 08:50:17 +0200 |
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committer | Peter Maydell | 2018-10-24 08:50:17 +0200 |
commit | 09cbd50198d5dcac8bea2e47fa5dd641ec505fae (patch) | |
tree | d232d47ca994e39ed722420e4d0cef8a576ea412 /target/arm/cpu.h | |
parent | target/arm: Convert division from feature bits to isar0 tests (diff) | |
download | qemu-09cbd50198d5dcac8bea2e47fa5dd641ec505fae.tar.gz qemu-09cbd50198d5dcac8bea2e47fa5dd641ec505fae.tar.xz qemu-09cbd50198d5dcac8bea2e47fa5dd641ec505fae.zip |
target/arm: Convert jazelle from feature bit to isar1 test
Having V6 alone imply jazelle was wrong for cortex-m0.
Change to an assertion for V6 & !M.
This was harmless, because the only place we tested ARM_FEATURE_JAZELLE
was for 'bxj' in disas_arm(), which is unreachable for M-profile cores.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181016223115.24100-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r-- | target/arm/cpu.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f1c2ec6461..1683ee98d6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1593,7 +1593,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ @@ -3160,6 +3159,11 @@ static inline bool isar_feature_arm_div(const ARMISARegisters *id) return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } +static inline bool isar_feature_jazelle(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; |