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| author | Richard Henderson | 2018-10-08 15:55:02 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-08 15:55:02 +0200 |
| commit | 0ab5953b00b3165877d00cf75de628c51670b550 (patch) | |
| tree | b43d07ca452159efd4cbc70c4412cbca1c1ad79f /target/arm/cpu.h | |
| parent | target/arm: Pass in current_el to fp and sve_exception_el (diff) | |
| download | qemu-0ab5953b00b3165877d00cf75de628c51670b550.tar.gz qemu-0ab5953b00b3165877d00cf75de628c51670b550.tar.xz qemu-0ab5953b00b3165877d00cf75de628c51670b550.zip | |
target/arm: Handle SVE vector length changes in system mode
SVE vector length can change when changing EL, or when writing
to one of the ZCR_ELn registers.
For correctness, our implementation requires that predicate bits
that are inaccessible are never set. Which means noticing length
changes and zeroing the appropriate register bits.
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65c0fa0a65..a4ee83dc77 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -910,6 +910,10 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); +void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el); +#else +static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } +static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) { } #endif target_ulong do_arm_semihosting(CPUARMState *env); |