diff options
| author | Richard Henderson | 2018-08-16 15:05:29 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:29:58 +0200 |
| commit | 0b62159be33d45d00dfa34a317c6d3da30ffb480 (patch) | |
| tree | 253ac99a8ac3073cdb2acdea41c0e08787808399 /target/arm/cpu.h | |
| parent | aspeed: add a max_ram_size property to the memory controller (diff) | |
| download | qemu-0b62159be33d45d00dfa34a317c6d3da30ffb480.tar.gz qemu-0b62159be33d45d00dfa34a317c6d3da30ffb480.tar.xz qemu-0b62159be33d45d00dfa34a317c6d3da30ffb480.zip | |
target/arm: Adjust FPCR_MASK for FZ16
When support for FZ16 was added, we failed to include the bit
within FPCR_MASK, which means that it could never be set.
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
Fixes: d81ce0ef2c4
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180810193129.1556-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a81f3d83cd..62c36b4150 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1269,7 +1269,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); * we store the underlying state in fpscr and just mask on read/write. */ #define FPSR_MASK 0xf800009f -#define FPCR_MASK 0x07f79f00 +#define FPCR_MASK 0x07ff9f00 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ |