diff options
| author | Mike Nawrocki | 2021-02-03 17:55:52 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-02-11 12:50:13 +0100 |
| commit | 10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5 (patch) | |
| tree | 409a37c68cd4d05d769b8fba6da5e6e26477b313 /target/arm/cpu.h | |
| parent | target/arm: Don't migrate CPUARMState.features (diff) | |
| download | qemu-10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5.tar.gz qemu-10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5.tar.xz qemu-10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5.zip | |
target/arm: Fix SCR RES1 handling
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.
The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.
Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
is supported at EL1 or above.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863..39633f73f3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4033,6 +4033,11 @@ static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; } +static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; |