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| author | Peter Maydell | 2019-06-14 12:44:57 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-06-17 16:15:06 +0200 |
| commit | 1120827fa182f0e76226df7ffe7a86598d1df54f (patch) | |
| tree | 35f39f957b3609984733a4daf3450af639eb2aba /target/arm/cpu.h | |
| parent | target/arm: Fix typos in trans function prototypes (diff) | |
| download | qemu-1120827fa182f0e76226df7ffe7a86598d1df54f.tar.gz qemu-1120827fa182f0e76226df7ffe7a86598d1df54f.tar.xz qemu-1120827fa182f0e76226df7ffe7a86598d1df54f.zip | |
target/arm: Only implement doubles if the FPU supports them
The architecture permits FPUs which have only single-precision
support, not double-precision; Cortex-M4 and Cortex-M33 are
both like that. Add the necessary checks on the MVFR0 FPDP
field so that we UNDEF any double-precision instructions on
CPUs like this.
Note that even if FPDP==0 the insns like VMOV-to/from-gpreg,
VLDM/VSTM, VLDR/VSTR which take double precision registers
still exist.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190614104457.24703-3-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a98c45b1ff..f9da672be5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3388,6 +3388,12 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; } +static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point */ + return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so |