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| author | Richard Henderson | 2020-06-26 05:31:30 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-06-26 15:31:12 +0200 |
| commit | 149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d (patch) | |
| tree | 029a1db5d13b8210b0f83ebfd1b500cac1e142ab /target/arm/cpu.h | |
| parent | target/arm: Tidy trans_LD1R_zpri (diff) | |
| download | qemu-149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d.tar.gz qemu-149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d.tar.xz qemu-149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d.zip | |
target/arm: Add arm_tlb_bti_gp
Introduce an lvalue macro to wrap target_tlb_bit0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb4f6ba69f..c54f0ab18a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3393,6 +3393,19 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; +/* Helper for the macros below, validating the argument type. */ +static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) +{ + return x; +} + +/* + * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. + * Using these should be a bit more self-documenting than using the + * generic target bits directly. + */ +#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in |