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| author | Abdallah Bouassida | 2018-05-18 18:48:07 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-05-18 18:48:07 +0200 |
| commit | 1f16378718fa87d63f70d0797f4546a88d8e3dd7 (patch) | |
| tree | 80933fd56dc43dc9e331c206c0444124d3bf5013 /target/arm/cpu.h | |
| parent | Merge remote-tracking branch 'remotes/famz/tags/docker-and-block-pull-request... (diff) | |
| download | qemu-1f16378718fa87d63f70d0797f4546a88d8e3dd7.tar.gz qemu-1f16378718fa87d63f70d0797f4546a88d8e3dd7.tar.xz qemu-1f16378718fa87d63f70d0797f4546a88d8e3dd7.zip | |
target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type
This is a preparation for the coming feature of creating dynamically an XML
description for the ARM sysregs.
A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML.
This bit is enabled automatically when creating CP_ANY wildcard aliases.
This bit could be enabled manually for any register we want to remove from the
dynamic XML description.
Signed-off-by: Abdallah Bouassida <abdallah.bouassida@lauterbach.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1524153386-3550-2-git-send-email-abdallah.bouassida@lauterbach.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3b086be570..c78ccabded 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1821,10 +1821,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. |