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| author | Richard Henderson | 2020-02-08 13:58:07 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-13 15:14:54 +0100 |
| commit | 220f508f49c5f49fb771d5105f991c19ffede3f7 (patch) | |
| tree | bfde4090bbd35912c5b5195e0e0a77cf0f2d8d10 /target/arm/cpu.h | |
| parent | target/arm: Introduce aarch64_pstate_valid_mask (diff) | |
| download | qemu-220f508f49c5f49fb771d5105f991c19ffede3f7.tar.gz qemu-220f508f49c5f49fb771d5105f991c19ffede3f7.tar.xz qemu-220f508f49c5f49fb771d5105f991c19ffede3f7.zip | |
target/arm: Update MSR access for PAN
For aarch64, there's a dedicated msr (imm, reg) insn.
For aarch32, this is done via msr to cpsr. Writes from el0
are ignored, which is already handled by the CPSR_USER mask.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200208125816.14954-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6dff1d55b..65a0ef8cd6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1186,6 +1186,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -1250,6 +1251,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_PAN (1U << 22) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) |