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| author | Peter Maydell | 2017-09-07 14:54:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-07 14:54:54 +0200 |
| commit | 334e8dad7a109d15cb20b090131374ae98682a50 (patch) | |
| tree | 2fba32a173c5a786c993ff609098e4403cd405e9 /target/arm/cpu.h | |
| parent | target/arm: Make MMFAR banked for v8M (diff) | |
| download | qemu-334e8dad7a109d15cb20b090131374ae98682a50.tar.gz qemu-334e8dad7a109d15cb20b090131374ae98682a50.tar.xz qemu-334e8dad7a109d15cb20b090131374ae98682a50.zip | |
target/arm: Make CFSR register banked for v8M
Make the CFSR register banked if v8M security extensions are enabled.
Not all the bits in this register are banked: the BFSR
bits [15:8] are shared between S and NS, and we store them
in the NS copy of the register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 03a47def00..41e270ccdb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -424,7 +424,7 @@ typedef struct CPUARMState { uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr; /* Configurable Fault Status */ + uint32_t cfsr[2]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar[2]; /* MemManage Fault Address */ @@ -1209,6 +1209,11 @@ FIELD(V7M_CFSR, NOCP, 16 + 3, 1) FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) +/* V7M CFSR bit masks covering all of the subregister bits */ +FIELD(V7M_CFSR, MMFSR, 0, 8) +FIELD(V7M_CFSR, BFSR, 8, 8) +FIELD(V7M_CFSR, UFSR, 16, 16) + /* V7M HFSR bits */ FIELD(V7M_HFSR, VECTTBL, 1, 1) FIELD(V7M_HFSR, FORCED, 30, 1) |