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| author | Richard Henderson | 2018-01-23 04:53:46 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-02-09 11:55:12 +0100 |
| commit | 3c7d30866fd1f56e5945726221410e0d8d535033 (patch) | |
| tree | 95ac18571e2b3612c02e20bb14a62299f1b472d2 /target/arm/cpu.h | |
| parent | target/arm: Expand vector registers for SVE (diff) | |
| download | qemu-3c7d30866fd1f56e5945726221410e0d8d535033.tar.gz qemu-3c7d30866fd1f56e5945726221410e0d8d535033.tar.xz qemu-3c7d30866fd1f56e5945726221410e0d8d535033.zip | |
target/arm: Add predicate registers for SVE
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180123035349.24538-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e3cd52aa3..966d2fdbb1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -188,6 +188,13 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; +/* In AArch32 mode, predicate registers do not exist at all. */ +#ifdef TARGET_AARCH64 +typedef struct ARMPredicateReg { + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); +} ARMPredicateReg; +#endif + typedef struct CPUARMState { /* Regs for current mode. */ @@ -515,6 +522,11 @@ typedef struct CPUARMState { struct { ARMVectorReg zregs[32]; +#ifdef TARGET_AARCH64 + /* Store FFR as pregs[16] to make it easier to treat as any other. */ + ARMPredicateReg pregs[17]; +#endif + uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; |