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| author | Peter Maydell | 2020-02-14 18:51:14 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-21 17:07:02 +0100 |
| commit | 4036b7d1cd9fb1097a5f4bc24d7d31744256260f (patch) | |
| tree | 05b452b3b5b20bbb4e9f9768b1e871913d20fab2 /target/arm/cpu.h | |
| parent | target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks (diff) | |
| download | qemu-4036b7d1cd9fb1097a5f4bc24d7d31744256260f.tar.gz qemu-4036b7d1cd9fb1097a5f4bc24d7d31744256260f.tar.xz qemu-4036b7d1cd9fb1097a5f4bc24d7d31744256260f.zip | |
target/arm: Use isar_feature function for testing AA32HPD feature
Now we have moved ID_MMFR4 into the ARMISARegisters struct, we
can define and use an isar_feature for the presence of the
ARMv8.2-AA32HPD feature, rather than open-coding the test.
While we're here, correct a comment typo which missed an 'A'
from the feature name.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-20-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ba97fc75c1..276030a5cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3526,6 +3526,11 @@ static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; } +static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; +} + /* * 64-bit feature tests via id registers. */ |