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| author | Richard Henderson | 2020-02-08 13:58:03 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-13 15:14:54 +0100 |
| commit | 437864216d63f052f3cd06ec8861d0e432496424 (patch) | |
| tree | 3bcc1114840244f67864a3d995175b2693f3f6f6 /target/arm/cpu.h | |
| parent | target/arm: Mask CPSR_J when Jazelle is not enabled (diff) | |
| download | qemu-437864216d63f052f3cd06ec8861d0e432496424.tar.gz qemu-437864216d63f052f3cd06ec8861d0e432496424.tar.xz qemu-437864216d63f052f3cd06ec8861d0e432496424.zip | |
target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask
CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED.
The function also takes into account bits that the cpu
does not support.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200208125816.14954-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08b2f5d73e..694b074298 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1209,8 +1209,6 @@ void pmu_init(ARMCPU *cpu); #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) /* Execution state bits. MRS read as zero, MSR writes ignored. */ #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) -/* Mask of bits which may be set by exception return copying them from SPSR */ -#define CPSR_ERET_MASK (~CPSR_RESERVED) /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ #define XPSR_EXCP 0x1ffU |