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| author | Richard Henderson | 2018-10-24 08:50:16 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-24 08:50:16 +0200 |
| commit | 47576b94af5c406fc6521fb336fb5c12beeac3f8 (patch) | |
| tree | 00b2785ea4822a27a306e3baeb4adfbc8585e377 /target/arm/cpu.h | |
| parent | target/arm: Add support for VCPU event states (diff) | |
| download | qemu-47576b94af5c406fc6521fb336fb5c12beeac3f8.tar.gz qemu-47576b94af5c406fc6521fb336fb5c12beeac3f8.tar.xz qemu-47576b94af5c406fc6521fb336fb5c12beeac3f8.zip | |
target/arm: Move some system registers into a substructure
Create struct ARMISARegisters, to be accessed during translation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181016223115.24100-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a314e557ac..e6ee509d0b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -795,13 +795,28 @@ struct ARMCPU { * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix * is used for reset values of non-constant registers; no reset_ * prefix means a constant register. + * Some of these registers are split out into a substructure that + * is shared with the translators to control the ISA. */ + struct ARMISARegisters { + uint32_t id_isar0; + uint32_t id_isar1; + uint32_t id_isar2; + uint32_t id_isar3; + uint32_t id_isar4; + uint32_t id_isar5; + uint32_t id_isar6; + uint32_t mvfr0; + uint32_t mvfr1; + uint32_t mvfr2; + uint64_t id_aa64isar0; + uint64_t id_aa64isar1; + uint64_t id_aa64pfr0; + uint64_t id_aa64pfr1; + } isar; uint32_t midr; uint32_t revidr; uint32_t reset_fpsid; - uint32_t mvfr0; - uint32_t mvfr1; - uint32_t mvfr2; uint32_t ctr; uint32_t reset_sctlr; uint32_t id_pfr0; @@ -815,21 +830,10 @@ struct ARMCPU { uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_mmfr4; - uint32_t id_isar0; - uint32_t id_isar1; - uint32_t id_isar2; - uint32_t id_isar3; - uint32_t id_isar4; - uint32_t id_isar5; - uint32_t id_isar6; - uint64_t id_aa64pfr0; - uint64_t id_aa64pfr1; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint64_t id_aa64isar0; - uint64_t id_aa64isar1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint32_t dbgdidr; |