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| author | Richard Henderson | 2020-06-26 05:31:05 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-06-26 15:31:12 +0200 |
| commit | 4b779cebb3e5ab30b945181f1ba3932f5f8a1cb5 (patch) | |
| tree | 478e26e0486429e13b2da142085dc59356b40d0c /target/arm/cpu.h | |
| parent | target/arm: Add DISAS_UPDATE_NOCHAIN (diff) | |
| download | qemu-4b779cebb3e5ab30b945181f1ba3932f5f8a1cb5.tar.gz qemu-4b779cebb3e5ab30b945181f1ba3932f5f8a1cb5.tar.xz qemu-4b779cebb3e5ab30b945181f1ba3932f5f8a1cb5.zip | |
target/arm: Add MTE system registers
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff70115801..0a98b6a06d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -502,6 +502,9 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ + uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; } cp15; struct { @@ -1282,6 +1285,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) #define PSTATE_UAO (1U << 23) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) |