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| author | Richard Henderson | 2018-05-18 18:48:08 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-05-18 18:48:08 +0200 |
| commit | 516e246a1a292f6c6f6aad5451799accbb08acd9 (patch) | |
| tree | 1efe89dee8519de1cff4d57a49a01126c9214d48 /target/arm/cpu.h | |
| parent | target/arm: Implement SVE predicate test (diff) | |
| download | qemu-516e246a1a292f6c6f6aad5451799accbb08acd9.tar.gz qemu-516e246a1a292f6c6f6aad5451799accbb08acd9.tar.xz qemu-516e246a1a292f6c6f6aad5451799accbb08acd9.zip | |
target/arm: Implement SVE Predicate Logical Operations Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 01281f5c56..df21e143cc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -541,6 +541,8 @@ typedef struct CPUARMState { #ifdef TARGET_AARCH64 /* Store FFR as pregs[16] to make it easier to treat as any other. */ ARMPredicateReg pregs[17]; + /* Scratch space for aa64 sve predicate temporary. */ + ARMPredicateReg preg_tmp; #endif uint32_t xregs[16]; @@ -548,7 +550,7 @@ typedef struct CPUARMState { int vec_len; int vec_stride; - /* scratch space when Tn are not sufficient. */ + /* Scratch space for aa32 neon expansion. */ uint32_t scratch[8]; /* There are a number of distinct float control structures: |