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| author | Peter Maydell | 2018-02-15 19:29:38 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-02-15 19:29:49 +0100 |
| commit | 57bb31568114023f67680d6fe478ceb13c51aa7d (patch) | |
| tree | 4a94b37381ab9c1b87f7df236ff857edd0963d81 /target/arm/cpu.h | |
| parent | target/arm: Migrate v7m.other_sp (diff) | |
| download | qemu-57bb31568114023f67680d6fe478ceb13c51aa7d.tar.gz qemu-57bb31568114023f67680d6fe478ceb13c51aa7d.tar.xz qemu-57bb31568114023f67680d6fe478ceb13c51aa7d.zip | |
target/arm: Implement v8M MSPLIM and PSPLIM registers
The v8M architecture includes hardware support for enforcing
stack pointer limits. We don't implement this behaviour yet,
but provide the MSPLIM and PSPLIM stack pointer limit registers
as reads-as-written, so that when we do implement the checks
in future this won't break guest migration.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-12-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bc0638d3fa..de62df091c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -498,6 +498,8 @@ typedef struct CPUARMState { uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; uint32_t scr[M_REG_NUM_BANKS]; + uint32_t msplim[M_REG_NUM_BANKS]; + uint32_t psplim[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: |