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| author | Rémi Denis-Courmont | 2021-01-12 11:44:58 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:51 +0100 |
| commit | 5ca192dfc551c8a40871c4e30a8b8ceb879adc31 (patch) | |
| tree | 725e2c332c941f40622099f0c146ce751aab2601 /target/arm/cpu.h | |
| parent | target/arm: factor MDCR_EL2 common handling (diff) | |
| download | qemu-5ca192dfc551c8a40871c4e30a8b8ceb879adc31.tar.gz qemu-5ca192dfc551c8a40871c4e30a8b8ceb879adc31.tar.xz qemu-5ca192dfc551c8a40871c4e30a8b8ceb879adc31.zip | |
target/arm: Define isar_feature function to test for presence of SEL2
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-6-remi.denis.courmont@huawei.com
[PMM: tweaked commit message to match reduced scope of patch
following rebase]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 66e3603294..22a3c8a4cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4011,6 +4011,11 @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; } +static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; |