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| author | Michael Davidsaver | 2017-06-02 12:51:48 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-06-02 12:51:48 +0200 |
| commit | 5dd0641d234e355597be62e5279d8a519c831625 (patch) | |
| tree | 9625608046d48707817e6366e71afff133921555 /target/arm/cpu.h | |
| parent | arm: All M profile cores are PMSA (diff) | |
| download | qemu-5dd0641d234e355597be62e5279d8a519c831625.tar.gz qemu-5dd0641d234e355597be62e5279d8a519c831625.tar.xz qemu-5dd0641d234e355597be62e5279d8a519c831625.zip | |
armv7m: Classify faults as MemManage or BusFault
General logic is that operations stopped by the MPU are MemManage,
and those which go through the MPU and are caught by the unassigned
handle are BusFault. Distinguish these by looking at the
exception.fsr values, and set the CFSR bits and (if appropriate)
fill in the BFAR or MMFAR with the exception address.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Message-id: 1493122030-32191-12-git-send-email-peter.maydell@linaro.org
[PMM: i-side faults do not set BFAR/MMFAR, only d-side;
added some CPU_LOG_INT logging]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/arm/cpu.h')
0 files changed, 0 insertions, 0 deletions