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authorPeter Maydell2017-02-28 13:08:17 +0100
committerPeter Maydell2017-02-28 13:08:17 +0100
commit7ecdaa4a9635f1ded0dfa9218c25273b6d4dcd44 (patch)
tree08f30c87a85aa83f9e683c39d926e35cbc1f2d34 /target/arm/cpu.h
parentarmv7m: Rewrite NVIC to not use any GIC code (diff)
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armv7m: Fix condition check for taking exceptions
The M profile condition for when we can take a pending exception or interrupt is not the same as that for A/R profile. The code originally copied from the A/R profile version of the cpu_exec_interrupt function only worked by chance for the very simple case of exceptions being masked by PRIMASK. Replace it with a call to a function in the NVIC code that correctly compares the priority of the pending exception against the current execution priority of the CPU. [Michael Davidsaver's patchset had a patch to do something similar but the implementation ended up being a rewrite.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 38a8e00908..649f237561 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1356,6 +1356,14 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure);
/* Interface between CPU and Interrupt controller. */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(void *opaque);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+ return true;
+}
+#endif
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);