diff options
| author | Richard Henderson | 2020-02-24 23:22:16 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-28 17:14:57 +0100 |
| commit | 7fbc6a403a0aab834e764fa61d81ed8586cfe352 (patch) | |
| tree | 99455bf524c7004aa9764ead4565751d98225866 /target/arm/cpu.h | |
| parent | cpu/arm11mpcore: Set number of GIC priority bits to 4 (diff) | |
| download | qemu-7fbc6a403a0aab834e764fa61d81ed8586cfe352.tar.gz qemu-7fbc6a403a0aab834e764fa61d81ed8586cfe352.tar.xz qemu-7fbc6a403a0aab834e764fa61d81ed8586cfe352.zip | |
target/arm: Add isar_feature_aa32_vfp_simd
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30e..a128d48d40 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; } +static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) +{ + /* + * Return true if either VFP or SIMD is implemented. + * In this case, a minimum of VFP w/ D0-D15. + */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ |