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| author | Peter Maydell | 2020-11-19 22:55:53 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:55 +0100 |
| commit | 83ff3d6add965c9752324de11eac5687121ea826 (patch) | |
| tree | 9b2a432d974acc6bb8ffddc3f0329c8111b023f8 /target/arm/cpu.h | |
| parent | target/arm: Don't clobber ID_PFR1.Security on M-profile cores (diff) | |
| download | qemu-83ff3d6add965c9752324de11eac5687121ea826.tar.gz qemu-83ff3d6add965c9752324de11eac5687121ea826.tar.xz qemu-83ff3d6add965c9752324de11eac5687121ea826.zip | |
target/arm: Implement VSCCLRM insn
Implement the v8.1M VSCCLRM insn, which zeros floating point
registers if there is an active floating point context.
This requires support in write_neon_element32() for the MO_32
element size, so add it.
Because we want to use arm_gen_condlabel(), we need to move
the definition of that function up in translate.c so it is
before the #include of translate-vfp.c.inc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-5-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5514c8286..11400a9d24 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3555,6 +3555,15 @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; } +static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) +{ + /* + * Return true if M-profile state handling insns + * (VSCCLRM, CLRM, FPCTX access insns) are implemented + */ + return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* Sadly this is encoded differently for A-profile and M-profile */ |