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| author | Peter Maydell | 2017-07-27 12:59:08 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-07-31 14:09:52 +0200 |
| commit | 8531eb4f614a60e6582d4832b15eee09f7d27874 (patch) | |
| tree | 64f9633ddee4973ae9674cabafa7c6f3472091c9 /target/arm/cpu.h | |
| parent | target/arm: Don't allow guest to make System space executable for M profile (diff) | |
| download | qemu-8531eb4f614a60e6582d4832b15eee09f7d27874.tar.gz qemu-8531eb4f614a60e6582d4832b15eee09f7d27874.tar.xz qemu-8531eb4f614a60e6582d4832b15eee09f7d27874.zip | |
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Almost all of the PMSAv7 state is in the pmsav7 substruct of
the ARM CPU state structure. The exception is the region
number register, which is in cp15.c6_rgnr. This exception
is a bit odd for M profile, which otherwise generally does
not store state in the cp15 substruct.
Rename cp15.c6_rgnr to pmsav7.rnr accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 102c58afac..b39d64aa0b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -305,8 +305,6 @@ typedef struct CPUARMState { uint64_t par_el[4]; }; - uint32_t c6_rgnr; - uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ @@ -519,6 +517,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; + uint32_t rnr; } pmsav7; void *nvic; |