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| author | Richard Henderson | 2017-09-12 15:50:01 +0200 |
|---|---|---|
| committer | Richard Henderson | 2018-02-08 16:54:06 +0100 |
| commit | 8b3495ea195503922c1e00253495cb6887b99dd5 (patch) | |
| tree | c6b6c8c746ae71bed6c977771bddad55967b2b61 /target/arm/cpu.h | |
| parent | tcg/optimize: Handle vector opcodes during optimize (diff) | |
| download | qemu-8b3495ea195503922c1e00253495cb6887b99dd5.tar.gz qemu-8b3495ea195503922c1e00253495cb6887b99dd5.tar.xz qemu-8b3495ea195503922c1e00253495cb6887b99dd5.zip | |
target/arm: Align vector registers
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d2bb59eded..8d41f783dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -492,7 +492,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - uint64_t regs[64]; + uint64_t regs[64] QEMU_ALIGNED(16); uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ |