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| author | Rémi Denis-Courmont | 2021-01-12 11:45:09 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:52 +0100 |
| commit | 926c1b97895879b78ca14bca2831c08740ed1c38 (patch) | |
| tree | 2a674ee6fc5e4922d867097311304ca011837cbb /target/arm/cpu.h | |
| parent | target/arm: revector to run-time pick target EL (diff) | |
| download | qemu-926c1b97895879b78ca14bca2831c08740ed1c38.tar.gz qemu-926c1b97895879b78ca14bca2831c08740ed1c38.tar.xz qemu-926c1b97895879b78ca14bca2831c08740ed1c38.zip | |
target/arm: Implement SCR_EL2.EEL2
This adds handling for the SCR_EL3.EEL2 bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Message-id: 20210112104511.36576-17-remi.denis.courmont@huawei.com
[PMM: Applied fixes for review issues noted by RTH:
- check for FEATURE_AARCH64 before checking sel2 isar feature
- correct the commit message subject line]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b115da5935..df0d677833 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2164,7 +2164,10 @@ static inline bool arm_is_secure(CPUARMState *env) static inline bool arm_is_el2_enabled(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL2)) { - return !arm_is_secure_below_el3(env); + if (arm_is_secure_below_el3(env)) { + return (env->cp15.scr_el3 & SCR_EEL2) != 0; + } + return true; } return false; } @@ -2211,7 +2214,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } - if (arm_feature(env, ARM_FEATURE_EL3)) { + if (arm_feature(env, ARM_FEATURE_EL3) && + ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); } |