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| author | Richard Henderson | 2020-02-07 15:04:22 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-07 15:04:22 +0100 |
| commit | 97fa9350017e647151dd1dc212f1bbca0294dba7 (patch) | |
| tree | 0ab2bab2d753d8526b8d2beb4a01ac6fe3f47758 /target/arm/cpu.h | |
| parent | target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* (diff) | |
| download | qemu-97fa9350017e647151dd1dc212f1bbca0294dba7.tar.gz qemu-97fa9350017e647151dd1dc212f1bbca0294dba7.tar.xz qemu-97fa9350017e647151dd1dc212f1bbca0294dba7.zip | |
target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2
The EL1&0 regime is the only one that uses 2-stage translation.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 272104afbb..c6da3d3043 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2911,7 +2911,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, - ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, @@ -2937,7 +2937,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1E3 = 1 << 3, ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE1 = 1 << 5, - ARMMMUIdxBit_S2NS = 1 << 6, + ARMMMUIdxBit_Stage2 = 1 << 6, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, ARMMMUIdxBit_MUserNegPri = 1 << 2, |