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| author | Peter Maydell | 2017-09-07 14:54:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-07 14:54:54 +0200 |
| commit | 9d40cd8a68cfc7606f4548cc9e812bab15c6dc28 (patch) | |
| tree | 5ea2b0c184445a132503a6ae8b8710be0e709fac /target/arm/cpu.h | |
| parent | target/arm: Make MPU_CTRL register banked for v8M (diff) | |
| download | qemu-9d40cd8a68cfc7606f4548cc9e812bab15c6dc28.tar.gz qemu-9d40cd8a68cfc7606f4548cc9e812bab15c6dc28.tar.xz qemu-9d40cd8a68cfc7606f4548cc9e812bab15c6dc28.zip | |
target/arm: Make CCR register banked for v8M
Make the CCR register banked if v8M security extensions are enabled.
This is slightly more complicated than the other "add banking"
patches because there is one bit in the register which is not
banked. We keep the live data in the NS copy of the register,
and adjust it on register reads and writes. (Since we don't
currently implement the behaviour that the bit controls, there
is nowhere else that needs to care.)
This patch includes the enforcement of the bits which are newly
RES1 in ARMv8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 29ffb2643d..d223446492 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -423,7 +423,7 @@ typedef struct CPUARMState { uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; - uint32_t ccr; /* Configuration and Control */ + uint32_t ccr[2]; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ |