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| author | Richard Henderson | 2019-02-15 10:56:41 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-15 10:56:41 +0100 |
| commit | a4d5846245c5e029e5aa3945a9bda1de1c3fedbf (patch) | |
| tree | 0c2f1bfef43d253eec7def5ddea82c7d26a515a1 /target/arm/cpu.h | |
| parent | target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] (diff) | |
| download | qemu-a4d5846245c5e029e5aa3945a9bda1de1c3fedbf.tar.gz qemu-a4d5846245c5e029e5aa3945a9bda1de1c3fedbf.tar.xz qemu-a4d5846245c5e029e5aa3945a9bda1de1c3fedbf.zip | |
target/arm: Split out FPSCR.QC to a vector field
Change the representation of this field such that it is easy
to set from vector code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190209033847.9014-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bfc05c796a..84ae6849c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -577,11 +577,13 @@ typedef struct CPUARMState { ARMPredicateReg preg_tmp; #endif - uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ + uint32_t qc[4] QEMU_ALIGNED(16); int vec_len; int vec_stride; + uint32_t xregs[16]; + /* Scratch space for aa32 neon expansion. */ uint32_t scratch[8]; @@ -1427,6 +1429,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ +#define FPCR_QC (1 << 27) /* Cumulative saturation bit */ static inline uint32_t vfp_get_fpsr(CPUARMState *env) { |