diff options
| author | Peter Maydell | 2017-09-07 14:54:52 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-07 14:54:52 +0200 |
| commit | acf949411ffb675edbfb707e235800b02e6a36f8 (patch) | |
| tree | ece985bec54622807e2847054c5eed67ec83ea52 /target/arm/cpu.h | |
| parent | target/arm: Add MMU indexes for secure v8M (diff) | |
| download | qemu-acf949411ffb675edbfb707e235800b02e6a36f8.tar.gz qemu-acf949411ffb675edbfb707e235800b02e6a36f8.tar.xz qemu-acf949411ffb675edbfb707e235800b02e6a36f8.zip | |
target/arm: Make BASEPRI register banked for v8M
Make the BASEPRI register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to
be restricted).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d93fe96e35..273abc3dc5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -72,6 +72,18 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +#define M_REG_NS 0 +#define M_REG_S 1 + /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 @@ -409,7 +421,7 @@ typedef struct CPUARMState { struct { uint32_t other_sp; uint32_t vecbase; - uint32_t basepri; + uint32_t basepri[2]; uint32_t control; uint32_t ccr; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ |