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| author | Rémi Denis-Courmont | 2021-01-12 11:45:06 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:52 +0100 |
| commit | b1a10c868f9b2b09e64009b43450e9a86697d9f3 (patch) | |
| tree | ed82e444c752f70c384c72d8d539158d57222cdf /target/arm/cpu.h | |
| parent | target/arm: generalize 2-stage page-walk condition (diff) | |
| download | qemu-b1a10c868f9b2b09e64009b43450e9a86697d9f3.tar.gz qemu-b1a10c868f9b2b09e64009b43450e9a86697d9f3.tar.xz qemu-b1a10c868f9b2b09e64009b43450e9a86697d9f3.zip | |
target/arm: secure stage 2 translation regime
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-14-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 53d0e989f0..235df64cd7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3096,6 +3096,9 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -3103,7 +3106,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, /* * M-profile. |