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| author | Peter Maydell | 2019-04-29 18:36:00 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-04-29 18:36:00 +0200 |
| commit | b593c2b81287040ab6f452afec6281e2f7ee487b (patch) | |
| tree | c5fccb99d4806afe49a25d6728e383c5ad6cfbb6 /target/arm/cpu.h | |
| parent | target/arm: Handle floating point registers in exception entry (diff) | |
| download | qemu-b593c2b81287040ab6f452afec6281e2f7ee487b.tar.gz qemu-b593c2b81287040ab6f452afec6281e2f7ee487b.tar.xz qemu-b593c2b81287040ab6f452afec6281e2f7ee487b.zip | |
target/arm: Implement v7m_update_fpccr()
Implement the code which updates the FPCCR register on an
exception entry where we are going to use lazy FP stacking.
We have to defer to the NVIC to determine whether the
various exceptions are currently ready or not.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190416125744.27770-12-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 67e4e95d44..eb989d773a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2045,6 +2045,20 @@ void armv7m_nvic_acknowledge_irq(void *opaque); */ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); /** + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) + * @opaque: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Return whether an exception is "ready", i.e. whether the exception is + * enabled and is configured at a priority which would allow it to + * interrupt the current execution priority. This controls whether the + * RDY bit for it in the FPCCR is set. + */ +bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); +/** * armv7m_nvic_raw_execution_priority: return the raw execution priority * @opaque: the NVIC * |