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| author | Richard Henderson | 2020-02-07 15:04:26 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-07 15:04:26 +0100 |
| commit | cc28fc30e333dc2f20ebfde54444697e26cd8f6d (patch) | |
| tree | 39918d91457e028c2b142294678c5e9d309a4825 /target/arm/cpu.h | |
| parent | target/arm: check TGE and E2H flags for EL0 pauth traps (diff) | |
| download | qemu-cc28fc30e333dc2f20ebfde54444697e26cd8f6d.tar.gz qemu-cc28fc30e333dc2f20ebfde54444697e26cd8f6d.tar.xz qemu-cc28fc30e333dc2f20ebfde54444697e26cd8f6d.zip | |
target/arm: Update get_a64_user_mem_index for VHE
The EL2&0 translation regime is affected by Load Register (unpriv).
The code structure used here will facilitate later changes in this
area for implementing UAO and NV.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d091a7e2e8..2ed2667a17 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,10 +3214,10 @@ typedef ARMCPU ArchCPU; * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | * | TBFLAG_ANY | |TBFLAG_M32| | - * | | +-------------------------| - * | | | TBFLAG_A64 | - * +--------------+-----------+-------------------------+ - * 31 20 14 0 + * | | +-+----------+--------------| + * | | | TBFLAG_A64 | + * +--------------+---------+---------------------------+ + * 31 20 15 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3283,6 +3283,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, UNPRIV, 14, 1) static inline bool bswap_code(bool sctlr_b) { |