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| author | Peter Maydell | 2020-02-14 18:51:01 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-21 17:07:01 +0100 |
| commit | ceb2744b47a1ef4184dca56a158eb3156b6eba36 (patch) | |
| tree | b2696539f2a6862a640b13309c4f5395d78adb83 /target/arm/cpu.h | |
| parent | target/arm: Factor out PMU register definitions (diff) | |
| download | qemu-ceb2744b47a1ef4184dca56a158eb3156b6eba36.tar.gz qemu-ceb2744b47a1ef4184dca56a158eb3156b6eba36.tar.xz qemu-ceb2744b47a1ef4184dca56a158eb3156b6eba36.zip | |
target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
where we currently have hard-coded bit values.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-7-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ef0feb228a..081955094d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1821,6 +1821,16 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) +FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) +FIELD(ID_AA64DFR0, TRACEVER, 4, 4) +FIELD(ID_AA64DFR0, PMUVER, 8, 4) +FIELD(ID_AA64DFR0, BRPS, 12, 4) +FIELD(ID_AA64DFR0, WRPS, 20, 4) +FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) +FIELD(ID_AA64DFR0, PMSVER, 32, 4) +FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) +FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) |