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| author | Richard Henderson | 2020-02-07 15:04:23 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-07 15:04:23 +0100 |
| commit | e013b7411339342aac8d986c5d5e329e1baee8e1 (patch) | |
| tree | 42aede089d141abcb76ccd262637c9020e32761b /target/arm/cpu.h | |
| parent | target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 (diff) | |
| download | qemu-e013b7411339342aac8d986c5d5e329e1baee8e1.tar.gz qemu-e013b7411339342aac8d986c5d5e329e1baee8e1.tar.xz qemu-e013b7411339342aac8d986c5d5e329e1baee8e1.zip | |
target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f01ec8dd2..a188398b03 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2907,7 +2907,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 = 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A, @@ -2933,7 +2933,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_0 = 1 << 0, ARMMMUIdxBit_E10_1 = 1 << 1, - ARMMMUIdxBit_S1E2 = 1 << 2, + ARMMMUIdxBit_E2 = 1 << 2, ARMMMUIdxBit_SE3 = 1 << 3, ARMMMUIdxBit_SE10_0 = 1 << 4, ARMMMUIdxBit_SE10_1 = 1 << 5, |