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| author | Peter Maydell | 2017-02-28 13:08:19 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-02-28 13:08:19 +0100 |
| commit | e13886e3a790b52f0b2e93cb5e84fdc2ada5471a (patch) | |
| tree | 5f76ff9d870ab65b2706330424754bc0d8a60040 /target/arm/cpu.h | |
| parent | armv7m: Check exception return consistency (diff) | |
| download | qemu-e13886e3a790b52f0b2e93cb5e84fdc2ada5471a.tar.gz qemu-e13886e3a790b52f0b2e93cb5e84fdc2ada5471a.tar.xz qemu-e13886e3a790b52f0b2e93cb5e84fdc2ada5471a.zip | |
armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
M profile doesn't implement ARM, and the architecturally required
behaviour for attempts to execute with the Thumb bit clear is to
generate a UsageFault with the CFSR INVSTATE bit set. We were
incorrectly implementing this as generating an UNDEFINSTR UsageFault;
fix this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 045830aeae..9e7b2dfc83 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_VFIQ 15 #define EXCP_SEMIHOST 16 /* semihosting call */ #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ +#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 |