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| author | Rémi Denis-Courmont | 2021-01-12 11:45:01 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:51 +0100 |
| commit | e9152ee91cc39ed8a53d03607e6e980a7e9444e6 (patch) | |
| tree | 59eca65e6b584bd41367e077ce4a32b2e44cdc51 /target/arm/cpu.h | |
| parent | target/arm: add MMU stage 1 for Secure EL2 (diff) | |
| download | qemu-e9152ee91cc39ed8a53d03607e6e980a7e9444e6.tar.gz qemu-e9152ee91cc39ed8a53d03607e6e980a7e9444e6.tar.xz qemu-e9152ee91cc39ed8a53d03607e6e980a7e9444e6.zip | |
target/arm: add ARMv8.4-SEL2 system registers
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-9-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc1ea586c1..53d0e989f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -168,6 +168,11 @@ typedef struct { uint32_t base_mask; } TCR; +#define VTCR_NSW (1u << 29) +#define VTCR_NSA (1u << 30) +#define VSTCR_SW VTCR_NSW +#define VSTCR_SA VTCR_NSA + /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -325,9 +330,11 @@ typedef struct CPUARMState { uint64_t ttbr1_el[4]; }; uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ + uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; TCR vtcr_el2; /* Virtualization Translation Control. */ + TCR vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register |