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| author | Peter Maydell | 2019-04-29 18:36:01 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-04-29 18:36:01 +0200 |
| commit | ea7ac69d124c94c6e5579145e727adec9ccbefef (patch) | |
| tree | bbfab88c96e2aca57c559f5c0a19797d0f8f919c /target/arm/cpu.h | |
| parent | target/arm: Move NS TBFLAG from bit 19 to bit 6 (diff) | |
| download | qemu-ea7ac69d124c94c6e5579145e727adec9ccbefef.tar.gz qemu-ea7ac69d124c94c6e5579145e727adec9ccbefef.tar.xz qemu-ea7ac69d124c94c6e5579145e727adec9ccbefef.zip | |
target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags
We are close to running out of TB flags for AArch32; we could
start using the cs_base word, but before we do that we can
economise on our usage by sharing the same bits for the VFP
VECSTRIDE field and the XScale XSCALE_CPAR field. This
works because no XScale CPU ever had VFP.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-18-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0ea448034b..99ccb4824d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3139,6 +3139,12 @@ FIELD(TBFLAG_A32, THUMB, 0, 1) FIELD(TBFLAG_A32, VECLEN, 1, 3) FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* + * We store the bottom two bits of the CPAR as TB flags and handle + * checks on the other bits at runtime. This shares the same bits as + * VECSTRIDE, which is OK as no XScale CPU has VFP. + */ +FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) +/* * Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! @@ -3147,10 +3153,6 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) -/* We store the bottom two bits of the CPAR as TB flags and handle - * checks on the other bits at runtime - */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ |