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| author | Cédric Le Goater | 2019-01-21 11:23:11 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-01-21 11:23:11 +0100 |
| commit | f16c845ade38444db62dc14eb5e267cc0c79876b (patch) | |
| tree | 056255a6b9fbae70677f1de0a0382855f85f73e7 /target/arm/cpu.h | |
| parent | target/arm: Allow Aarch32 exception return to switch from Mon->Hyp (diff) | |
| download | qemu-f16c845ade38444db62dc14eb5e267cc0c79876b.tar.gz qemu-f16c845ade38444db62dc14eb5e267cc0c79876b.tar.xz qemu-f16c845ade38444db62dc14eb5e267cc0c79876b.zip | |
ftgmac100: implement the new MDIO interface on Aspeed SoC
The PHY behind the MAC of an Aspeed SoC can be controlled using two
different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and
PHYDATA (MAC64) are involved but they have a different layout.
BIT31 of the Feature Register (MAC40) controls which MDC/MDIO
interface is active.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190111125759.31577-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
0 files changed, 0 insertions, 0 deletions