diff options
| author | Peter Maydell | 2020-02-14 18:51:16 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-21 17:07:02 +0100 |
| commit | f6287c24c66d6b9187c1c2887e1c7cfa4d304b0c (patch) | |
| tree | 2158afddaa15dbd24bad7d5b5e117abe2b6d1e0e /target/arm/cpu.h | |
| parent | target/arm: Use FIELD_EX32 for testing 32-bit fields (diff) | |
| download | qemu-f6287c24c66d6b9187c1c2887e1c7cfa4d304b0c.tar.gz qemu-f6287c24c66d6b9187c1c2887e1c7cfa4d304b0c.tar.xz qemu-f6287c24c66d6b9187c1c2887e1c7cfa4d304b0c.zip | |
target/arm: Correctly implement ACTLR2, HACTLR2
The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7
or the original ARMv8. They were later added as optional registers,
whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2
they are mandatory (ie ID_MMFR4.AC2 must be non-zero).
We implemented HACTLR2 in commit 0e0456ab8895a5e85, but we
incorrectly made it exist for all v8 CPUs, and we didn't implement
ACTLR2 at all.
Sort this out by implementing both registers only when they are
supposed to exist, and setting the ID_MMFR4 bit for -cpu max.
Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72
CPU models; this is correct, because those CPUs do not implement
this register.
Fixes: 0e0456ab8895a5e85
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-22-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6af3290ca..b4c83a1cb5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3531,6 +3531,11 @@ static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; } +static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; +} + /* * 64-bit feature tests via id registers. */ |