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| author | Richard Henderson | 2020-02-07 15:04:23 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-07 15:04:23 +0100 |
| commit | fba37aedecb82506c62a1f9e81d066b4fd04e443 (patch) | |
| tree | 846bd0ef3a924876e6e0d60e537f9dee703cd652 /target/arm/cpu.h | |
| parent | target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* (diff) | |
| download | qemu-fba37aedecb82506c62a1f9e81d066b4fd04e443.tar.gz qemu-fba37aedecb82506c62a1f9e81d066b4fd04e443.tar.xz qemu-fba37aedecb82506c62a1f9e81d066b4fd04e443.zip | |
target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01]
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the Secure EL1&0 regime.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index afc3e76ce5..6cf2b3d6fd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2909,8 +2909,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, @@ -2935,8 +2935,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_1 = 1 << 1, ARMMMUIdxBit_S1E2 = 1 << 2, ARMMMUIdxBit_S1E3 = 1 << 3, - ARMMMUIdxBit_S1SE0 = 1 << 4, - ARMMMUIdxBit_S1SE1 = 1 << 5, + ARMMMUIdxBit_SE10_0 = 1 << 4, + ARMMMUIdxBit_SE10_1 = 1 << 5, ARMMMUIdxBit_Stage2 = 1 << 6, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, |